In the integrated circuit (IC) industry, trench isolation, especially shallow trench isolation (STI), is now being used to replace conventional local oxidation of silicon (LOCOS). Shallow trench isolation is preferred since STI forms improved field isolation structures what have reduced bird's beak active area encroachment, improved device-to-device and well-to-well isolation, and improved latchup avoidance. However, the dielectric material used to fill STI isolation trenches that are formed within a substrate may be substantially eroded during post-trench processing.
This trench fill erosion results in one or more of: (1) adverse sidewall parasitic MOSFET devices being formed adjacent the active areas of an integrated circuit (IC); (2) reduced gate oxide integrity and reliability due to 90.degree. sharp corners of the trench being incorporated into the desired MOS gate stack (this also greatly reduces the reliability of any nonvolatile memory (NVM) device made in these active areas); (3) various polysilicon stringer problems; (4) uncontrollable threshold voltage (Vt) variations from device-to-device and wafer-to-wafer; (5) "kinks" in MOSFET IV curves when operating in the linear MOS region; and (6) increased junction leakage current. Furthermore, the erosion of the trench fill material can be worsened by 2.times. or 3.times. in microcontrollers (MCUs) or digital signal processors (DSPs) that have two or three active areas that each use different active area or sacrificial oxide preparation and surface processing. For example, one MCU substrate may contain a floating gate EEPROM array, power MOSFETs, and high speed logic devices all formed on same chip in different active areas. Each of these areas may need different active area preparation and gate oxidization wherein the last area processed has been exposed to many RCA cleans, sac oxides, HF strips, etc., many of which will erode the trench fill material adjacent this last active area. For a 5000 angstrom deep trench, trench fill erosion of greater than 1000 angstroms has been experimentally observed in these mixed-signal multiple-active-area MCU and DSP devices.
FIGS. 1-5 specifically illustrate the trench erosion problem that occurs when conventional shallow trench isolation (STI) is used in integrated circuits (ICs).
FIG. 1 illustrates a conventional semiconductor trench structure 110. In FIG. 1, a semiconductor substrate or semiconductor wafer 112 is provided. A pad oxide or thermal oxide layer 114 is formed over the substrate 112. A thicker silicon nitride layer 116 is typically deposited on top of the thin oxide layer 114 to function as a hard mask. Conventional photolithographic processing is used to etch an opening 118 through the silicon nitride layer 16 and the oxide layer 114 to expose a top surface portion of the substrate 112. This opening in the dielectric layers 114 and 116 is then extended into the substrate by a silicon etch to form a shallow trench region 118, as shown in FIG. 1. After formation of the shallow trench region 118, a thermal oxidation process is utilized to form a thin oxide liner layer 117 on both the sidewalls and the bottom surface of the trench 118 in FIG. 1.
FIG. 2 illustrates that a trench fill layer 120a is conformally deposited within the trench 118 after formation of the liner 117. Layer 120a is typically formed as a tetraethylorthosilicate (TEOS) layer and is formed having a thickness much greater than a thickness of the silicon nitride layer 116. FIG. 2 illustrates a dashed line 119 within the layer 120a. Line 119 indicates a level to which the layer 120a will be subsequently polished to form a proper trench fill plug region using the silicon nitride layer 116 as a polish stop layer.
FIG. 3 illustrates the structure of FIG. 2 after chemical mechanical polishing (CMP) planarization of layer 120a of FIG. 2 has occurred. The CMP process forms a trench plug region 120b from the layer 120a illustrated previously in FIG. 2. As indicated in FIG. 3, a top surface 119 of the plug region 120b is roughly analogous to the dashed line 119 in FIG. 2. After chemical mechanical polishing (CMP) is complete, the silicon nitride layer 116, which is used as a chemical mechanical polish (CMP) stop, is then removed by a wet etch process that is very selective to oxide. After removal of the silicon nitride layer 116, at least one active area, indicated as active area 124, is defined at a top surface of the substrate 112 in FIG. 3. Electrical devices are subsequently formed within the active area 124 of the substrate 112 and interconnected by overlying conductive layers to form a functional IC.
FIG. 4 illustrates the adverse erosion of the trench fill plug 120b which occurs from subsequent processing of the active area 124 to form the active devices. After formation of the trench plug 120b in FIG. 3, the active area 124 is exposed to one or more etch processing steps, sacrificial oxide steps, and surface cleaning steps which will erode the dielectric plug material 120b over time. It is known in the art that TEOS layers will etch in oxide etch environments faster than thermally grown oxide layers. This faster etch rate of TEOS when compared to thermal oxide (e.g., gate oxides and most sacrificial oxides) will further exacerbate the erosion of the plug region 120b compared to other IC regions since the trench plug 120b is typically made of the faster-etching TEOS material.
FIG. 4 illustrates a plug region 120c which is the plug region 120b of FIG. 3 after being substantially eroded by subsequent semiconductor active area processing that is needed to make active circuitry in the region 124. As illustrated in FIG. 4, erosion of the plug to result in an eroded plug 120c forms an exposed sidewall 126 of the active silicon surface area 124. This sidewall area 126 is exposed to subsequent active area processing (e.g., gate oxide formation and gate polysilicon formation) whereby unwanted parasitic sidewall devices (e.g., an unwanted sidewall parasitic MOSFET) are formed on the sidewall 126 of the active area 124. Furthermore, the channel doping along this sidewall is such that the parasitic sidewall MOSFET will turn on before the top-surface planar MOSFET is turned on, thereby creating a "kink" in the Id-Vds characteristics of the MOSFET of FIG. 5 when the MOSFET is attempting to operate in the linear MOS region.
FIG. 5 illustrates a three-dimensional cross-sectional perspective of the device of FIG. 4. FIG. 5 illustrates the top surface of the active area 124 of FIG. 4 as well as the parasitic sidewall 126 which is adversely formed by trench fill erosion. FIG. 5 illustrates that a MOSFET source region 128 and a MOSFET drain region 130 are formed within the active area by conventional ion implantation and thermal activation. These source and drain region 128 and 130 are separated by a channel region 132 within the active area 124. As is known in the art, a gate dielectric layer (not specifically shown in FIG. 5) is formed over the channel region 132 and a conductive gate electrode (not specifically shown in FIG. 5) is then formed overlying this gate oxide and overlying the channel region 132. The gate electrode is used to control a conductivity of the channel region 132 between the current electrode regions 128 and 130 in FIG. 5.
Unfortunately, due to the erosion present in the trench plug region 120c, a parasitic MOSFET sidewall channel region 134 is present in the structure of FIG. 5 once the gate electrode is formed. Due to the fact that parasitic channel region 134 will be exposed to gate oxide formation and lie adjacent a portion of a subsequently formed gate electrode, the channel region 134 is a parasitic transistor channel region which is formed between the electrodes 128 and 130 in parallel to the desired channel region 132. Due to the fact that threshold (Vt) adjust implants, well region doping profiles, and other implanted regions are formed from the surface of the substrate, doping concentrations of dopant atoms in the substrate are not constant throughout the depth of the semiconductor substrate 112. Therefore, the threshold voltage of the vertical sidewall channel region 134 may be substantially different from a threshold voltage of the top channel region 132. Typically, a doping concentration of the region 134 integrated over the vertical sidewall will be greater or lesser than a doping concentration at the active area surface 132 depending upon the processing sequence. Therefore, the parasitic channel region 134 is likely to typically "turn on" and form a conductive inversion region (i.e., an unwanted parasitic leakage path) between the regions 128 and 130 before the actual transistor channel region 132 is "turned-on" creating undesirable MOSFET behavior.
In addition, if the sidewall of the channel region 134 of FIG. 5 is deep along the substrate sidewall 126, the likelihood of forming adverse polysilicon stringers when patterning polysilicon gate electrodes also increases. In addition, the erosion ensures that a 90.degree. corner of silicon substrate (at a top of the sidewall 126 of FIG. 4) is thermally oxidized and incorporated into the final MOSFET gate stack. These sharp corners affect oxide breakdown voltage and adversely affect MOS lifetime, reliability, and performance. Increased junction leakage is also found due to the erosion shown in FIGS. 4-5. Therefore, this parasitic channel region 134 is disadvantageous altogether.
Note that the erosion of the sidewall is substantially worsened when multiple transistor devices having different gate oxides are formed in different parts of an IC substrate. Today, it is desired to integrate many different devices (e.g., bipolar devices, logic MOSFETs, floating gate devices, high voltage MOSFET, etc.) together on the same integrated circuit (IC). If a surface among N surfaces is repeatedly exposed to N surface cleans, sacrificial oxidations, and the like, where N is a finite positive integer, the erosion of the trench adjacent this surface is worsened roughly by the factor of N. In other words, trench erosion of 350 Angstroms for a single gate oxide IC may easily be 1000 Angstroms or more for a device requiring three different gate oxide regions on the same die. Therefore, the trench erosion problem is extremely damaging to multiple gate oxide ICs that involve mixed technology (as typically found in modern microcontrollers (MCUs) and digital signal processors (DSPs)).
One way to reduce the adverse erosion of the trench region 20c as illustrated in FIG. 5 is to expose the trench region 120c to fewer etch environments. The prior art has attempted to reduce the amount of wet etching and reactive ion etching (RIE) of the trench fill material 120c by reducing the amount of processing in the active area 124. However, for each etch and/or clean process removed from the overall semiconductor flow, the active area 124 is not being fully or adequately processed in accordance with general IC processing standards. As a result, integrated circuit (IC) yield in the active area and/or IC performance may be adversely impacted due to reduced surface-clean processing and reduced active area etch processing. In any event, this reduction in active area cleaning and preparation does not truly prevent erosion, but merely attempts to reduce its severity.
Another solution attempted in the prior art is to form the liner 117 of FIG. 1 from a silicon nitride layer or a silicon oxynitride layer. This silicon nitride liner 117 will not etch substantially in oxide/TEOS etch environments and will not etch substantially in substrate cleaning processes. Therefore, through use of this nitrided liner, the sidewall erosion of the trench fill material 120c may be reduced by the sidewall presence of silicon nitride or oxynitride 117. However, silicon nitride, in contact with a silicon substrate, has been shown to cause stress induced defects near the active area which adversely impacts MOSFET devices. Furthermore, any deposition of additional material within the trench may change the aspect ratio of the trench opening 118 thereby adversely affecting subsequent deposition processing and trench filling.
Also, if the trench fill erosion were still to occur (as is likely the case if the nitride liner is surrounded by TEOS trench fill) the exposed sidewall 126 of FIG. 4 would be covered with the silicon nitride liner 117. This silicon nitride liner is most likely non-oxidizable. Therefore, a sidewall parasitic MOSFET having a thin silicon nitride gate oxide layer (with a dielectric permittivity roughly twice that of thermal oxide) will be formed. This parasitic device may actually create more damaging sidewall parasitic MOSFET behavior than the sidewall parasitic MOSFET that results from the use of the conventional thermal oxidized trench liners as in FIGS. 4-5. In addition, the presence of both exposed oxide surfaces and exposed nitride surfaces when forming the trench layer 120a in FIG. 2 adversely affects the conformality and selectivity of the TEOS deposition process of FIG. 2. Therefore, the increased complexity and risk from using a nitride or nitrided trench fill liner is not always advantageous. In any event, this "solution" does not prevent trench fill erosion but merely attempts to reduce its severity.
In another embodiment, a polysilicon layer may be deposited within the trench 118 formed in FIG. 1 whereby this polysilicon fill can be thermally oxidized to form a polysilicon-oxide liner 117 in the hope of reducing sidewall erosion of the region 120c. Note that polysilicon-oxide (polyox) is similar to thermal oxide in that it etches slower than conventional TEOS liners which could reduce overall trench erosion over time. However, this process adds at least one other process step to the process flow (e.g., it adds at least the additional step of the deposition of the polysilicon), and may decrease a lateral dimension of the trench whereby filling of the trench via subsequent dielectric deposition processing is more complicated. In any event, this does not prevent erosion but merely attempts to reduce its severity.
Some prior art trench processes form conductive or semiconductive trench fills such as silicon germanium or polysilicon. These conductive or semiconductive trench fill regions are then oxidized so that no overlying conductive layers (such as gate polysilicon) contact or capacitively couple to these conductive fill regions. These oxide capped semiconductive filled trench regions are dangerous to use when erosion is a severe problem. If the oxide on top of the semiconductive or conductive trench fill erodes, then increased capacitive coupling, loss of effective device-to-device isolation, and electrical short circuiting of layers may occur in addition to all of the erosion disadvantages taught above with respect to FIGS. 1-5.
Therefore, a need exists in the industry for a shallow trench isolation process that eliminates or substantially retards trench fill erosion. It would be even more advantageous if this process would enable mixed signal, or multiple active area MCUs or DSPs to be formed without the hazards of trench fill erosion.